Conventionally, SOI (Silicon on Insulator) substrates, which are silicon substrates in which a monocrystalline silicon layer is formed on a surface of an insulating layer, are known in the art. Forming devices, such as transistors, on the SOI substrates can reduce parasitic capacitance and increase electric resistance. That is, higher device performance and integration can be obtained. The insulating layer is made of, e.g., a silicon oxide film (SiO2).
In order to increase the operating speed of the devices, and further reduce the parasitic capacitance, it is desirable to reduce the thickness of the monocrystalline silicon layer of the SOI substrates. In general, various methods, such as those using mechanical polishing or chemical mechanical polishing (hereinafter referred to as “CMP”), or using porous silicon, are known as methods for forming an SOI substrate.
For example, in a method proposed as an example of a method for forming an SOI substrate by hydrogen implantation, after a hydrogen implanted layer is formed by implanting hydrogen into a semiconductor substrate, and the semiconductor substrate is bonded with another substrate, a heat treatment is performed so that a part of the semiconductor substrate is separated from the other substrate along the hydrogen implanted layer, and the remaining part of the semiconductor substrate is transferred to the other substrate, thereby forming a semiconductor layer (see Non-Patent Document 1, Non-Patent Document 2, and the like). An SOI substrate, in which a very thin monocrystalline silicon layer is formed on the surface of an insulating layer, can be formed by this method.
Moreover, in another known method, after a monocrystalline silicon layer is formed on an insulating substrate, such as a glass substrate, by the method of transferring a part of a semiconductor substrate to another substrate, monocrystalline silicon TFTs (Thin Film Transistors) are formed by the monocrystalline silicon layer (see, e.g., Patent Document 1). According to this method, since the TFTs are formed after the monocrystalline silicon layer is formed on the surface of the insulating substrate, a gate oxide film needs to be formed on the surface of the monocrystalline silicon layer formed on the insulating substrate (that is, on the separated surface formed by the hydrogen implantation).
However, the surface of the monocrystalline silicon layer, formed on the insulating substrate by transferring a part of the semiconductor substrate, has relatively high surface roughness (concaves and convexes on the surface). Thus, it is difficult to form a high quality gate oxide film, and to form high performance TFTs. Moreover, TFTs need to be finely fabricated after forming the monocrystalline silicon layer on the insulating substrate.
Thus, the applicant has proposed a method for forming a thin device portion on another substrate. In this method, after a device portion having devices, such as monocrystalline silicon TFTs, is formed on a semiconductor substrate, and a hydrogen implanted layer is formed in the semiconductor substrate, the device portion is bonded with the other substrate, and a part of the semiconductor substrate is separated, thereby forming a thin device portion on the other substrate (see, e.g., Patent Document 2).
The device portion has: a plurality of conductive films, which are formed adjacent to each other on the surface of a planarizing layer that at least partially covers the monocrystalline silicon TFTs; and an insulating film that covers the plurality of conductive layers, and the device portion is bonded with the other substrate by using the surface of the insulating layer as a bonding surface. According to this method, since monocrystalline silicon TFTs are formed in advance on the semiconductor substrate, no gate oxide film needs to be formed on the separated surface formed by the hydrogen implantation, and high performance monocrystalline silicon TFTs can be formed. Moreover, since microfabrication of the TFTs is performed on the semiconductor substrate, the same level of dimensional reduction as that achieved by state-of-the-art microfabrication accuracy of silicon LSI (Large Scale Integration) can in principle be implemented without being subject to the limitations of microfabrication accuracy on insulating substrates. Moreover, using a transparent substrate as the other substrate enables the semiconductor device having a thin semiconductor layer to be applied to LCD devices.
Thus, reliable bonding between the device portion and the glass substrate is required in the case of forming the device portion on the other substrate by bonding the device portion, formed on the semiconductor substrate, with the other substrate. In order to reliably bond the device portion and the other substrate together, it is desirable that both the device portion and the other substrate have very flat bonding surfaces. Thus, the surface of the insulating layer is planarized by a CMP method in order to improve the flatness of the bonding surface of the device portion.    Patent Document 1: Japanese Published Patent Application No. 2003-234455    Patent Document 2: Japanese Published Patent Application No. 2005-26472    Non-Patent Document 1: Electronics Letters, Vol. 31, No. 14, 1995, pp. 1201-1202    Non-Patent Document 2: Jpn. J. Appl. Phys. Vol. 36 (1997), pp. 1636-1641